Digital phase-locked loop

ABSTRACT

A digital phase-locked loop with a digitally controlled oscillator is disclosed. The phase difference between a reference phase and a phase derived from the output phase of the oscillator is determined by a phase detector device and converted into a corresponding digital set value. The digital set value from the phase detector device is fed through a digital filter, to the digitally controlled oscillator, for the corresponding setting of the output phase thereof. By means of the above architecture any digital loop filter may be used.

FIELD OF INVENTION

The present invention relates to a digital phase-locked loop forgenerating a clock signal with the aid of a digitally controlledoscillator (DCO), the clock signal having a defined phase and frequencyrelationship with a reference clock signal.

BACKGROUND

The present invention relates to a digital phase-locked loop forgenerating a clock signal with the aid of a digitally controlledoscillator (DCO), the clock signal having a defined phase and frequencyrelationship with a reference clock signal.

The use of analog phase-locked loops (PLLs) is known for generatingfrequencies which are synchronized with a specific reference frequency.An analog phase-locked loop of this type is disclosed for example in thedocument F. M. Gardner, “Charge-Pump Phase-Locked Loops”, IEEE Trans.Comm. Vol. 28, pp. 1849-1858, November 1980. This analog phase-lockedloop comprises a phase/frequency detector (PFD), which compares theoutput clock of a voltage-controlled oscillator (VCO) with a referenceclock and generates as output signal voltage pulses which contain theinformation of the phase and frequency difference between the outputclock of the voltage-controlled oscillator and the reference clock. Thevoltage pulses are fed to a charge pump which converts the voltagepulses into corresponding current pulses, these current pulses, fortheir part, being integrated by a first- or higher-order transimpedanceloop filter. Finally, the voltage-controlled oscillator is driven by theoutput signal of the loop filter in order to set its output clockaccordingly. A divider can be arranged in the feedback path between thevoltage-controlled oscillator and the phase/frequency detector so thatthe output clock of the voltage-controlled oscillator divided by afactor N is fed to the phase/frequency detector, where N may be anarbitrary positive number. In the adjusted state of the phase-lockedloop, the output frequency of the voltage-controlled oscillator thuscorresponds to N times the reference frequency.

If a high frequency resolution with little jitter is demanded, the useof a digitally controlled oscillator (DCO) is advantageous. In thisrespect, various phase-locked loop architectures have been proposed, thecharge pumps and loop filters always having been realized with analogcomponents heretofore.

Thus, by way of example, the document J. Chiang, H. Chen, “A 3.3 alldigital phase locked loop with small DCO hardware and fast phase lock”,Proceedings of the 1998 IEEE International Symposium on Circuits andSystems, ISCAS '98, Vol. 1, discloses a digital phase-locked loopwherein, instead of the analog phase/frequency detector, a digital phasedetector and a digital frequency detector provided separately therefromare used. The complexity of the overall system is increased as a result.Moreover, the minimum resolution is generally poorer when using digitalphase or frequency detectors than when using analog phase or frequencydetectors. Furthermore, this document proposes using a control logic ofthe digitally controlled oscillator which is connected between thedigital phase and frequency detectors and the digitally controlledoscillator. Said control logic performs specific control sequences whichcan be generalized only with considerable effort if at all, so that thedigital phase-locked loop described in this document is not suitable fordifferent applications.

U.S. Pat. No. 5,162,746 A also discloses a digital phase-locked loopwherein a digital phase detector is used in combination with an up/downcounter and the output signal of the up/down counter is fed via anappropriately configured decoder to a digitally controlled oscillatorfor the purpose of correspondingly setting its output clock.

A further digital phase-locked loop is described in the document M.Izumikawa, M. Yamashina, “Compact realization of Phase-Locked loop usingdigital control”, IEICE Trans. Electron., Vol. E80-C, No. 4, April 1997,wherein, instead of a digitally controlled oscillator, an analog,voltage-controlled oscillator is used whose output clock is comparedwith a reference clock by a numerical phase detector. The digitalcontrol signal generated by the numerical phase detector is fed via adigital loop filter to a digital/analog converter in order to convertthe digital control values into corresponding analog control values forthe voltage-controlled oscillator. In this case, the number of digitalcontrol values corresponds to the frequency resolution of thisphase-locked loop.

The previously proposed architectures for a phase-locked loop with adigitally controlled oscillator make it more difficult to effect astability analysis of the phase-locked loop, or even make said analysisimpossible, since the transfer function of the loop filter respectivelyused and hence the phase and gain stability limits of the phase-lockedloop can be varied only with considerable effort, if at all, by thedeveloper. Thus, the loop filter transfer function best suited to therespectively desired application cannot be chosen freely.

SUMMARY

Therefore, the present invention is based on the object of proposing adigital phase-locked loop with a digitally controlled oscillator whichmakes it possible to use an arbitrary digital loop filter, so that thedeveloper can always choose the transfer function best suited to therespective application.

In particular, the intention is for the phase detector device to convertthe temporally concentrated phase difference information into a phaseinformation item that is distributed over the time axis in the form of anumerical digital control value which can then be integrated in asuitable manner in the digital loop filter.

In order to achieve the object mentioned above, the invention proposes agenerally valid structure for a phase-locked loop with a digitallycontrolled oscillator. The digital phase-locked loop according to theinvention comprises a digitally controlled oscillator for generating aspecific output clock, a phase detector device for detecting the analogphase difference between the output clock of the digitally controlledoscillator and a reference clock and for converting the analog phasedifference thus detected into a corresponding digital control value forthe digitally controlled oscillator, and also a digital loop filter viawhich the digital control value of the phase detector device is fed tothe digitally controlled oscillator for the purpose of correspondinglysetting its output clock.

The phase detector device of the digital phase-locked loop according tothe invention can thus be a phase/frequency analog-to-digital converter(PFDC) which quantizes the phase and frequency information obtained bythe comparison of the output clock of the digitally controlledoscillator with the reference clock, in such a way that, unlike inconventional analog charge pump phase-locked loops, it is no longerconcentrated in short current or voltage pulses, but rather is convertedinto a digital control value and distributed uniformly along the timeaccess. The advantage of this solution is that the charge pump can beobviated and the analog loop filter can be replaced by any desired typeof a digital loop filter. The developer can thus choose the digital loopfilter with the transfer function that is best suited to therespectively desired application. With the aid of the present invention,the entire phase-locked loop can be considered in a traditional mannerlike an all-analog system and be analyzed in particular with regard toits stability, in which case the phase and gain stability limits can becalculated and varied in a simple manner. The digital loop filter cansubsequently be developed with the aid of conventional techniques as areplacement for a time-continuous filter. By way of example, an IIRfilter, an FIR filter, a digital wave filter or a bilineartransformation filter, etc. can be used as the digital loop filter.

Overall, the development of the phase-locked loop is thus significantlysimplified. The essentially digital design strategy represents a clearadvantage since the transfer of the circuit design to smaller chips ormore modern technologies is significantly simplified and accelerated andthe chip area respectively required can be significantly reduced inparticular for the case of very low resonant frequencies.

However, the principle is not restricted to integrated circuits, butrather can also be applied to any desired control loops, e.g. controlloops constructed in a discrete fashion.

One or more frequency dividers can be arranged in the feedback path ofthe phase-locked loop according to the invention. Equally, the referencefrequency can be divided down by one or more frequency dividers beforeit is fed to the phase detector device according to the invention.

The use of a digitally controlled oscillator means that the presentinvention is suitable, in particular, for all applications of frequencysynthesis where a high frequency resolution with little jitter isdesired.

The present invention is described in more detail below using apreferred exemplary embodiment with reference to the drawing.

DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a simplified block diagram of a digital phase-locked loopin accordance with a preferred exemplary embodiment of the presentinvention,

FIG. 2 shows the construction of a phase detector device shown in FIG.1,

FIG. 3 shows a representation for illustrating the method of operationof the phase detector device shown in FIG. 1 and FIG. 2,

FIG. 4 shows the construction of an edge detector shown in FIG. 2, and

FIG. 5 shows the construction of a quantizer shown in FIG. 2.

DETAILED DESCRIPTION

The digital phase-locked loop shown in FIG. 1 comprises, as essentialcomponents, a phase/frequency detector device 1 configured as aphase/frequency analog-to-digital converter (PFDC), a matching digitalloop filter 2 and a digitally controlled oscillator (DCO). Furthermore,in the exemplary embodiment shown in FIG. 1, a frequency divider 4 isprovided in the feedback path, which frequency divider divides theoutput frequency f of the digitally controlled oscillator 3 by thedivider factor 1/N, where N may be an arbitrary positive number. Afurther frequency divider 5 with the divider factor 1/M may additionallybe provided. A further frequency divider 6 with the divider ratio 1/Mmay also be provided for the reference clock or the reference frequencyf_(ref) of the phase detector device 1. The two frequency dividers 5 and6 are advantageous in particular when the operating clock frequencyf_(s) of the phase detector device 1 and of the digital loop filter 2 isnot sufficiently higher than the frequency clock frequency f_(ref).

In the exemplary embodiment shown in FIG. 1 the reference clock f_(ref)is divided down by the frequency divider 6 with the divider factor 1/Mand then fed as input signal I1 to the phase detector device 1. Thephase detector device 1 receives, as further input signal I2, the outputclock f of the digitally controlled oscillator 3, which output clock haspreviously been divided down by the frequency dividers 4 and 5 with thedivider factors 1/N and 1/M, respectively. The phase detector device 1detects the phase difference between the two input signals I1 and I2,quantizes it in a suitable manner and thus converts the phase differenceinto a numerical digital control value which is fed to the digital loopfilter 2 via a bus having a suitable bus width n_(SA). The architectureof the digital loop filter 2 is completely independent of theconfiguration of the phase detector 1. The digital output value of thedigital loop filter 2 is fed to the digitally controlled oscillator 3via a further bus having the bus width n_(DF) in order thus tocorrespondingly set or control its output frequency f directly.

As has already been mentioned, in principle, any desired type of digitalfilter of any desired order can be used as the digital loop filter 2.Thus, the digital loop filter 2 may be configured for example as an FIRfilter (“Finite Impulse Response”), IIR filter (“Infinite ImpulseResponse”) or as a digital wave filter. The concrete configuration ofthe digital loop filter 2 is left to the respective responsibledeveloper, depending on the stability requirements, the resonantfrequency, etc. The digitally controlled oscillator 3, too, can inprinciple be configured as desired. The sole task of the digitallycontrolled oscillator 3 is to generate an output frequency f which isproportional to its digital input value. If a high frequency resolutionwith little jitter is required, the digitally controlled oscillator 3may be configured as a crystal oscillator, for example.

One possible construction of the phase detector device 1 shown in FIG. 1is illustrated in detail in FIG. 2. In this case, the phase detectordevice 1 essentially comprises an analog phase/frequency detector (PFD),an edge detector (ED), a quantizer or sampler (SA) and an arithmeticadder 9, which adds the output values of the edge detector 7 and of thequantizer 8 by means of two's complement addition. In this case, theadder 9 is provided with a limit for preventing an overflow.

The phase/frequency detector 24 is a conventional analog phase/frequencydetector which compares the two input signals I1 and I2 with one anotherand, depending on the phase difference between these two input signalsI1 and I2, generates pulsed output signals UP and DOWN, which can assumeeither a high level (corresponding to the binary value “1”) or a lowlevel (corresponding to the binary “0”). The pulse width of the UP andDOWN pulses contains the information about the phase/frequencydifference with respect to the input signals I1 and I2. The outputsignals of the phase/frequency detector 24 are in each case fed to theedge detector 7 and the quantizer 8.

The task of the quantizer 8 is to convert the “temporally concentrated”phase difference information of the phase/frequency detector 24 into aphase difference information item that is “distributed” over the timeaxis in the form of a numerical digital control value which can then beintegrated in a suitable manner in the digital loop filter 2 (cf. FIG.1).

This means in other words that the combination comprising thephase/frequency detector 24 and the quantizer 8 digitally simulates thebehavior of an “ideal” analog phase detector. This also becomes clearfrom the representation of FIG. 3, which illustrates on the one hand theoutput signal of an ideal phase detector and on the other hand theoutput signal of the quantizer 8 and also the output signal of thephase/frequency detector 24 as a function of time. As can be seen fromFIG. 3, the output signal of the quantizer 8 can be regarded as atemporally sampled version of the output signal of an ideal phasedetector. This concept enables the design of the phase-locked loop to besignificantly simplified since the entire phase-locked loop can beconsidered in a traditional manner as an all-analog system and thedigital loop filter 2 can be selected in a simple manner with the aid ofconventional techniques. FIG. 3 also reveals how the pulse width of thepulses generated by the phase/frequency detector 24 decreases as thereduction of the phase error Δφ increases.

The quantizer 8 is operated completely synchronously with the digitalclock signal f_(s), so that the minimum phase resolution of thequantizer 8 is defined by the ratio between the reference frequencyf_(ref) divided by the divider 6 and the operating frequency f_(s). Ifthe divider ratio of the dividers 5 and 6 is designated by 1/M and thedivider ratio 4 by 1/N and if it is assumed that the operating frequencyf_(s) of the quantizer 8 corresponds to twice the output frequency f ofthe digitally controlled oscillator 3 (which can be achieved in a simplemanner with a small digital circuit), then the minimum phase resolutionis defined as follows: ${\Delta\quad\phi} = \frac{1}{2\quad M\quad N}$

The divider factors M and N can thus be utilized to improve the minimumphase resolution of the quantizer 8. If N=64 and M=8, for example, thenthe minimum phase resolution Δφ=1/1024, which is comparable to theresolution of a 10-bit A/D converter. As will be described in evengreater detail below, the range of values of the quantizer 8 is [−2MN+1,2MN−1], the minimum number of output bits of the quantizer 8 includedthe sign bit being defined as follows:n _(SA)=log₂(2MN)+1

The insertion of the additional frequency dividers 5 and 6 reduces thegain of the open phase-locked loop by M. However, this can becompensated for simply by means of a suitable choice of the gain of thedigital loop filter 2.

The operation of the quantizer 8 will be explained in more detail belowwith reference to FIG. 5, FIG. 5 illustrating one possible structure ofthe quantizer 8.

As is shown in FIG. 5, the two output signals UP and DOWN of thephase/frequency detector 24 are sampled with the aid of registers 12 and13, the respectively mutually corresponding samples of the two signalsbeing subtracted by a subtractor 14 in order to obtain an intermediatesignal Ud, which can assume the values 1, 0 and −1. The signal Ud is apulsed signal whose shape is similar to the shape of the signals UP andDOWN. The pulse length of the individual pulses of the signal Ud is ameasure of the phase difference between the two input signals I1 and I2of the phase/frequency detector 24.

The first sample of each Ud pulse is removed by a simple digital circuit15, so that the resultant signal Ud1 is fed to the input of an up/downcounter 16. The counter 16 alters its counter reading in a mannerdependent on the respective value of the signal Ud1, the counter readingbeing incremented or decremented if the signal Ud1 is positive ornegative, respectively, while the counter reading remains unchanged ifthe signal Ud1 is zero. The output value supplied by this up/downcounter 16 at the end of each pulse thus corresponds simply to thesigned length of the Ud1 pulses, where the output value of the up/downcounter 16 can lie in the range −2MN+1 and 2MN−1.

FIG. 5 also illustrates a circuit section with an absolute value formingunit 18, a logic NOT element 19, a register 20, a logic AND element 21and a logic OR element 22, the AND element 21 generating a reset pulsewhenever a Ud1 pulse is past, and applying to a reset input of theup/down counter 16 in order to reset the counter reading to zero again.Furthermore, an enable pulse is applied to an enable terminal of anoutput register 17 via the output of the OR element 22 after each Ud1pulse, so that the final result of the up/down counter 16 is output asthe output value. This output value is maintained until a new Ud1 pulseoccurs.

FIG. 5 additionally illustrates a monitoring circuit 23 in order toremove the last output value of the quantizer 8 or the up/down counter16 (in the adjusted state of the phase-locked loop, the signal Ud1permanently assumes the value zero, so that only the edge detector7—shown in FIG. 2—of the phase detector device 1 operates, while thestate of the quantizer 8 does not change). The monitoring circuit 23 canbe realized in a simple manner in the form of a counter which is resettogether with the up/down counter 16 and otherwise continuously countsup. If, taking account of an acceptable tolerance limit, the counterreading of this counter 23 exceeds the value 2MN (which means that thesignal Ud1 has no pulses), then an enable pulse is generated and thelast output value of the register 17 is replaced by the value zero.

If the phase-locked loop is almost in the adjusted state, the phaseresolution of the quantizer 8 does not suffice. In this case, the pulsesgenerated by the phase/frequency detector 24 shown in FIG. 2 are soshort that they can hardly be sampled by the quantizer 8. Therefore, inaccordance with FIG. 2, the circuit block 7 designated as edge detectoris provided in order to further improve the phase resolution and thus,in particular, the operation in the adjusted state of the phase-lockedloop. One possible construction of the edge detector 7 is illustrated inFIG. 4.

As is shown in FIG. 4, the edge detector 7 comprises two circuit blocks10 and 11. The circuit block 10 designated as pulse detector receivesthe UP and DOWN pulses of the phase/frequency detector 24 as inputsignals. Whenever a pulse occurs at one of the inputs of the pulsedetector 10, the pulse detector 10 ascertains whether firstly an UPpulse or a DOWN pulse has occurred. The pulse detector 10 then generatesan individual pulse whose duration corresponds to the clock period ofthe digital clock signal f_(s), this individual pulse assuming the value“1” for example, if an UP pulse first occurred, while the individualpulse assumes the value “−1” if a DOWN pulse first occurred. If no pulsewas detected at the inputs of the pulse detector 10, the individualpulse generated by the pulse detector 10 has the value zero. Theindividual pulse generated by the pulse detector 10 thus contains anitem of information about which of the two pulsed signals UP and DOWNleads, and can be used to slightly correct the digital control value fedto the digital loop filter 2.

For this purpose, the individual pulse generated by the pulse detector10 is expanded to a duration of L clock periods of the digital clocksignal f_(s). The circuit block 11 can be realized by a first-order combfilter, for example. The factor L may be programmable and assume valuesbetween 1 and MN. This measure improves the minimum resolution by thefactor L/MN, so that the minimum phase resolution is defined as follows:${\Delta\quad\phi} = {\frac{1}{2\quad M\quad N} \cdot \frac{L}{M\quad N}}$

If, by way of example, N=64, M=8 and L=8, then Δφ=1/65536 results forthe minimum phase resolution, which is comparable to the resolution of a16-bit A/D converter.

As is shown in FIG. 2, the digital correction value generated by theedge detector 7 in this way is added by the adder 9 to the digitalcontrol value generated by the quantizer 9, so that the resultantdigital summation value is fed as final control value to the digitalloop filter 2 shown in FIG. 1 and then to the digitally controlledoscillator 3 for correspondingly setting the output frequency f thereof.

1. A digital phase-locked loop comprising: a digitally controlledoscillator for generating an output clock signal; a phase detectordevice for detecting an analog phase difference between a dependentclock, which is digitally dependent on the output clock signal, and areference clock, the phase detector device converting the detectedanalog phase difference into a corresponding digital control value forthe digitally controlled oscillator, the phase detector device having: aphase detector generating a first pulse signal and a second pulse signaldependent on the analog phase difference, a pulse of the first pulsesignal being generated if the dependent clock is slower than thereference clock, and a pulse of the second pulse signal being generatedif the dependent clock is faster than the reference clock; and aquantizing device for converting the information contained in the pulsesof the first and second pulse signals for the phase difference into thecorresponding digital control value; the quantizing device having afirst circuit section for sampling the first and second pulse signalsand for subtracting the samples of the first and second pulse signals togenerate a corresponding digital difference value, and a counter whosecounter reading is altered in a manner dependent on the respectivelygenerated digital difference value of the first circuit section, thecounter reading serving as a basis for the digital control value; and adigital loop filter through which the digital control value of the phasedetector device connects to the digitally controlled oscillator to setthe output clock signal.
 2. The phase-locked loop of claim 1, furthercomprising a frequency divider for connecting the output clock signal tothe phase detector device.
 3. The phase-locked loop of claim 1, furthercomprising a frequency divider for connecting the reference clock to thephase detector device via at least one frequency divider.
 4. Thephase-locked loop of claim 1, wherein the digitally controlledoscillator comprises a crystal oscillator.
 5. The phase-locked loop ofclaim 1, wherein the quantizing device further comprises: a secondcircuit section configured to monitor the digital difference valuesignal generated by the first circuit section for the end of a pulse andto generate a reset for the counter for resetting the counter readingthereof; and an output register through which an instantaneous counterreading of the counter is output, the output register being activatedwhen the reset signal of the second circuit section is present.
 6. Thephase-locked loop of claim 5, wherein the quantizing device furthercomprises a third circuit section configured to detect an absence ofpulses in the digital difference value signal generated by the firstcircuit section and to replace a last digital value output by the outputregister by the value zero.
 7. The phase-locked loop of claim 1, whereinthe phase detector device further comprises: a pulse detector deviceconfigured to monitor the occurrence of pulses of the first pulse signaland of the second pulse signal and to generate a digital correctionvalue depending on whether a pulse occurs in the first pulse signal orin the second pulse signal; and an addition device for receiving thedigital correction value from the pulse detector device, receiving thedigital control value from the quantizing device, and adding the digitalcorrection value to the digital output value to generate a resultantdigital summation value to be provided to the digital loop filter. 8.The phase-locked loop of claim 7, wherein the pulse detector device isconfigured to generate the digital correction value in the form of apulse signal with a programmable pulse length.